Navraj Nandra joined Synopsys in February 2005 as Director of Product Marketing for the mixed-signal products that include SERDES, USB and DDR2. He has worked in the semiconductor industry since the mid 80's as an analog/mixed signal IC designer for Philips Semiconductors, austriamicrosystems, (San Jose & Austria) and EM-Marin (Switzerland). He has been responsible for the complete design of a number of analog front ends in application areas such as digital audio, RFID and automotive. He joined Synopsys from Barcelona Design where he was Director of Application Engineering. During his four years at Barcelona he was responsible for pre- and post-sales support for Barcelona's analog synthesis technology. Navraj holds a masters degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University. He has presented at numerous technical conferences on mixed-signal design, analog IP and analog synthesis/EDA.
Anwar Awad is the senior director of mixed-signal IP development at Synopsys, including high-speed serdes, USB PHYs, IO and high-speed memory interfaces. Anwar received a MSEE from SUNY at Stony Brook in 1989 and has 17 years industry experience. He’s worked with semiconductor IP since 1991 at Silicon Architects where he helped with the innovation of Silicon libraries. Anwar has been involved in hard IP development since 0.8u to 65nm. Anwar is also responsible for wireless USB RF and digital IP products. In addition to mixed-signal IP, Anwar’s expertise is in design flow and integration for SoC including IEM (Intelligent Energy Management) chip and flow. His experience includes working at Toshiba electronics for DFT flow and libraries for high-end ASIC.
John T. Stonick received his Ph.D. in ECE from North Carolina State U. in 1992. From 1993-1997 he held a postdoctoral research position in the ECE department at Carnegie Mellon University. From 1997-2000, he was an assistant professor with the ECE department at Oregon State University and a co-director for the NSF Center for the Design of Analog-Digital Integrated Circuits (CDADIC). Starting in 2000 he was a principal design engineer with Accelerant Networks until they were acquired by Synopsys in 2004. Since 2004 he has remained with Synopsys where he holds the title of Synopsys Scientist, was a Top Inventor in 2004 and 2005 and the 2004 Synopsys Distinguished Inventor. He is a member of the IEEE and a member of the IEEE ISSCC 2006-7 technical program committee (wireline). He has been a co-author on 2 IEEE best paper awards, 2006 IEEE CICC Best Invited Paper and 1994 Matti S. Sukola Award for Best Paper Presented at the IEEE Broadcast Symposium, and a co-author on a paper which won DesignCon Paper Award in 2006. His interests include system architecture and simulation, clock and data recovery, using adaptive digital techniques to compensate for analog circuit imperfections in wireless and wireline transceivers.
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